August 2026 · Semiconductor manufacturing · Verified real-world result

SEMICONDUCTOR MASK SYNTHESIS 6×24

Six candidate photomasks against six co-resident logics on IBM Heron r2 · ibm_kingston · 156 qubits. One coupled job on the public ICCAD-2013 benchmark. Pre-registered industry ranking: ILT over no-OPC. QPC raw readout: no-OPC 0.622 over ILT 0.460.

Plain English

What this case is: Every chip is printed through a photomask. At these dimensions light bends, so the mask is a computed distortion that makes the wafer print right. That is called optical proximity correction, and at 1nm-class nodes it is one of the heaviest computations in manufacturing. Inverse lithography goes furthest: treat the mask as a variable and solve for whatever shape prints best.
Why classical methods split: A mask is judged on six things that pull in different directions: print accuracy, edge placement, tolerance to dose and focus drift, the thinnest feature the mask writer can resolve, the thinnest gap, and how many exposures the writer must fire. Industry practice adds these into one weighted score and descends, so each run sees one weighting of a six-way conflict. On our frozen panel the dependence is total: under equal weighting doing nothing ranks first and the inverse lithography mask ranks last; under the published print-quality objective the order is exactly reversed.
What we expected (locked before the run): We pre-registered the industry expectation before IBM submit. Published inverse lithography practice on this benchmark holds that the optimised mask W0.00 is the better mask, so the locked claim was that it outranks doing nothing.
What QPC computed: One job on ibm_kingston (Heron r2), 147 architecture qubits carried on the full 156-qubit register, 4096 shots, raw counts primary, public job ID below.
Headline result: Verified ranking on raw counts. Doing nothing scores 0.622 against the inverse lithography mask at 0.460. Held together in one computation, the optimised mask loses print-quality rank because it buys its print quality with 30,060 width violations, 12,796 space violations and 1,130 writer shots against zero, zero and sixteen.
What this delivers: A checkable finding for a mask shop, on a public benchmark, in numbers they already compute. Architecture research on a frozen public benchmark anyone can re-run.

Verdict

MASK-E1 scored on raw counts. QPC ranked no-OPC over the published ILT mask.

QPC ranked no correction above the inverse lithography mask on coupled raw score, by 0.162. The run is readable: deviation from the noiseless simulation of the identical circuit is 0.036, which is 22 percent of the decision margin.

0.622

No OPC, coupled raw

0.460

ILT mask, coupled raw

0.162

Decision margin

22%

Chip noise vs margin

Why this counts as a real result

A live manufacturing question: is optical proximity correction worth its manufacturability cost.
Public ICCAD-2013 M1 benchmark. Every metric computed locally, nothing taken from a paper table.
Expectation written, and the panel hash-locked, before IBM submit.
Classical methods completely reverse each other on this panel, so no single weighting is neutral.
The coupled ranking differs from the classical average, and the uncoupled control on the same chip reproduces that average exactly.
A readability gate is enforced in code: hardware deviation is measured against the decision margin.

Method	Order on the pair
Published ILT objective (print quality only)	ILT mask > no OPC (ILT ranks 1st overall, no OPC 5th)
Equal weight over all six logics	no OPC > ILT mask (no OPC ranks 1st overall, ILT last)
QPC coupled raw (this job)	no OPC > ILT mask. QPC coupled raw

The locked pair, in manufacturing numbers

Measured on layout M1_test1, at mask rules calibrated to the tightest geometry present in the ten targets (57 nm width, 51 nm space).

Measurement	No OPC	ILT mask	Which wins
Pattern error (L2)	114,478	48,300	ILT
Edge placement violations	83	8	ILT
Process window (PV band)	45,815	54,518	No OPC
Mask width violations	0	30,060	No OPC
Mask space violations	0	12,796	No OPC
Writer shots	16	1,130	No OPC

Two logics to four. The inverse lithography mask prints far better and is far harder to build. Which one wins depends entirely on a weighting a human chose, which is why the decision belongs in one coupled computation rather than in a scalarisation.

Full QPC ranking (six masks, raw coupled)

Rank	Mask recipe	Score	Print	Window	Buildability
1	no OPC, ship the target	0.622	0.203	0.613	0.904
2	shrink 4 nm	0.607	0.126	0.824	0.856
3	grow 4 nm, x only	0.564	0.283	0.319	0.834
4	ILT, window-weighted	0.463	0.854	0.126	0.314
5	ILT mask (published optimum)	0.460	0.870	0.088	0.310
6	grow 8 nm	0.447	0.297	0.404	0.562

The industry finding is the locked pair. The table is the full coupled readout on the frozen panel. Grow 8 nm sits fourth under the classical average and last under the coupled computation, and it is the only candidate with no strong column anywhere. Holding the logics together penalises being mediocre at everything, which a weighted sum leaves unexpressed.

The coupled ranking is its own computation

The uncoupled variant is initialisation only: the classical equal-weight average expressed as a quantum state, the right control. It ran on the same chip in the same job family and reproduced the classical equal-weight order exactly. The coupled variant returned its own ranking.

Mask recipe	Uncoupled rank	Coupled rank
grow 8 nm	4	6
ILT, window-weighted	5	4
ILT mask	6	5

The same moves appear in noiseless simulation and on hardware, so they are the coupling, not the chip.

Readability gate

QPC measures chip deviation against the decision margin and enforces the threshold in code.

The published verdict is job daas1burrl7c73860bd0: 21 bridges, depth 147 after routing, deviation 0.036, which is 22 percent of the 0.162 margin. If hardware deviation from the noiseless simulation of the identical circuit exceeds the margin, the scoring code returns VOID. An earlier Kingston circuit at depth 845 is on the public record as daarp96rrl7c738600f0. The replacement job is the architecture result.

Job record

Field	Value
Backend	IBM Heron r2 · `ibm_kingston` · 156 qubits
Job ID	`daas1burrl7c73860bd0`
Shots	4096
Geometry	6 masks × 24 contextures + 3 junctions = 147 architecture qubits, padded to the full 156Q register · RYY bridges · no_cross control
Contextures	6 metrics × 4 ICCAD-2013 M1 layouts. 15 independent columns against a bar of 15
Primary metric	MASK-E1 locked pair on coupled raw score. Readability gate: margin must exceed deviation from the noiseless simulation
Panel SHA256	`73d7dfd1743fc577a3fb2fee66b1005ba1c12ebbfb007234d46e9ce501f01d08`
Noiseless reference (same lock)	no OPC 0.634 > ILT 0.466; margin 0.168
ISA depth	147 after routing, 96 two-qubit gates, 21 cross-context bridges
Readability sidecar	`daarp96rrl7c738600f0` (depth 845, on record) · published verdict `daas1burrl7c73860bd0`
Architecture sidecar	`daarpcbvpcac73dcu0a0`, junction gap 0.0049 on raw counts
QPU time	19.75 seconds total across all three jobs
Data source	ICCAD-2013 CAD Contest Problem 3, M1 layouts (public benchmark). Printed-image metrics through a numpy reimplementation of the OpenILT lithography model, 24 optical kernels, three process corners. Mask-domain metrics computed on the masks themselves at rules calibrated from the ten targets. Every cell is computed from the frozen layouts and the hardware counts.
Label	Architecture research on a frozen public benchmark anyone can re-run.